Senior Engineer Flip Chip Packaging Location: Dholera Gujarat
Employment Type: Full-Time
Industry: Semiconductor Manufacturing / Advanced Packaging
Experience: 5 10 Years
Role Overview The Senior Engineer Flip Chip Packaging will lead the development qualification and manufacturing ramp of advanced flip chip packaging technologies. This role focuses on FC-BGA and FC-CSP process ownership new product introduction failure analysis and process control in a high-reliability semiconductor manufacturing environment.
Key Responsibilities -
Define develop and sustain Flip Chip (FC-BGA FC-CSP) packaging processes
-
Own bump formation solder reflow and underfill process development
-
Lead New Product Introduction (NPI) activities from bump design through package qualification
-
Analyze and resolve interconnect and package-level failures using advanced FA techniques
-
Work closely with substrate vendors and bumping equipment suppliers for process alignment
-
Establish process control plans SPC charts and FMEA for flip chip production lines
-
Support customer qualification reliability validation and technical reviews
-
Independently address customer technical issues related to flip chip packaging
-
Mentor junior engineers and drive cross-functional process improvement initiatives
-
Ensure compliance with JEDEC and IPC packaging standards
Required Qualifications -
B.E./ in Materials Science Electronics Metallurgy or related engineering disciplines
-
5 10 years of hands-on experience in advanced IC packaging within OSAT or IDM environments
-
Strong understanding of solder bump technology UBM structures and substrate design rules
-
Experience with capillary underfill (CUF) and molded underfill (MUF) materials
-
Knowledge of thermal management warpage and co-planarity requirements for high-density packages
-
Hands-on failure analysis experience using C-SAM X-ray cross-sectioning SEM-EDX
-
Ability to work independently with cross-functional teams including design reliability and manufacturing
Preferred / Additional Experience -
Exposure to Flip Chip WLP or advanced BGA platforms
-
Experience with automotive telecom or high-performance compute packaging
-
Knowledge of 2.5D / 3D IC integration HBM or TSV processes
#LI-GT1
Senior Engineer Flip Chip Packaging Location: Dholera Gujarat Employment Type: Full-Time Industry: Semiconductor Manufacturing / Advanced Packaging Experience: 5 10 Years Role Overview The Senior Engineer Flip Chip Packaging will lead the development qualification and manufacturing ramp o...
Senior Engineer Flip Chip Packaging Location: Dholera Gujarat
Employment Type: Full-Time
Industry: Semiconductor Manufacturing / Advanced Packaging
Experience: 5 10 Years
Role Overview The Senior Engineer Flip Chip Packaging will lead the development qualification and manufacturing ramp of advanced flip chip packaging technologies. This role focuses on FC-BGA and FC-CSP process ownership new product introduction failure analysis and process control in a high-reliability semiconductor manufacturing environment.
Key Responsibilities -
Define develop and sustain Flip Chip (FC-BGA FC-CSP) packaging processes
-
Own bump formation solder reflow and underfill process development
-
Lead New Product Introduction (NPI) activities from bump design through package qualification
-
Analyze and resolve interconnect and package-level failures using advanced FA techniques
-
Work closely with substrate vendors and bumping equipment suppliers for process alignment
-
Establish process control plans SPC charts and FMEA for flip chip production lines
-
Support customer qualification reliability validation and technical reviews
-
Independently address customer technical issues related to flip chip packaging
-
Mentor junior engineers and drive cross-functional process improvement initiatives
-
Ensure compliance with JEDEC and IPC packaging standards
Required Qualifications -
B.E./ in Materials Science Electronics Metallurgy or related engineering disciplines
-
5 10 years of hands-on experience in advanced IC packaging within OSAT or IDM environments
-
Strong understanding of solder bump technology UBM structures and substrate design rules
-
Experience with capillary underfill (CUF) and molded underfill (MUF) materials
-
Knowledge of thermal management warpage and co-planarity requirements for high-density packages
-
Hands-on failure analysis experience using C-SAM X-ray cross-sectioning SEM-EDX
-
Ability to work independently with cross-functional teams including design reliability and manufacturing
Preferred / Additional Experience -
Exposure to Flip Chip WLP or advanced BGA platforms
-
Experience with automotive telecom or high-performance compute packaging
-
Knowledge of 2.5D / 3D IC integration HBM or TSV processes
#LI-GT1
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